1. Field of the Invention
The present invention relates to multi-layer integrated circuits (3D integrated circuits) and in particular to the positions at which vertical interconnects may be positioned to provide connections between different layers.
2. Description of the Prior Art
Three-dimensional integrated circuits in which two or more layers of active electronic components are integrated both vertically and horizontally into a single extended circuit have recently been developed. Stacking two-dimensional dies and connecting them in the third dimension reduces the footprint of the integrated circuit and can allow the close integration of different circuit types, wherein the layers which form the stack can each be built with different processes. In addition, the vertical dimension increases the possibilities for providing connections between the components of the integrated circuit.
The layers of a three-dimensional integrated circuit may be built up in various ways, such as by manufacturing essentially two-dimensional electronic components on two or more semiconductor wafers which are then aligned and bonded together. This bonding may for example be carried out using by a pattern of copper bond points provided on a face of a semiconductor wafer, such that two wafers with this pattern can each be ground to a smooth surface (for example by chemical mechanical polishing (CMP)) and fused together.
One notable consequence in the present context of using such a technique for bonding layers of the three-dimensional integrated circuits together is that these copper bond points also define the positions at which a vertical interconnect, which couples components in one layer to components in the next, may validly be placed.
FIG. 1 schematically illustrates a side view of a wafer layer 10 having a front face 11 and a back face 12 each of which are partially formed by a set of copper bond points 13 and 14 respectively. It will be understood that viewed from above, these copper bond points form a pattern of shapes (for example, octagons) which extend across the wafer surfaces. The wafer 10 itself comprises a silicon oxide sub-layer 20 and a silicon crystal sub-layer 22. At the interface between the silicon oxide sub-layer 20 and the silicon sub-layer 22 are formed the transistors (transistor layer 24) which comprise the logical components of this layer of the integrated circuit. Within the silicon oxide sub-layer 20 are stacked metal layers 26 which provide the interconnections between the logical components of this portion of the integrated circuit. Also shown in FIG. 1 is a through-silicon-via (TSV) connecting one of the metal layers 26 in silicon oxide sub-layer 20 to one of the copper bond points 14 at the back face 12 of the layer. Accordingly, it will be understood that in setting out the layout of an integrated circuit within a layer such as that illustrated in FIG. 1, the system designer is constrained to place any TSVs such that they align with the positions of the copper bond points 14 on the back face 12 to which the TSV connects.
This type of constraint applies at each layer of a multi-layer three-dimensional integrated circuit, in that the system designer is constrained to place “vertical interconnects” (which may be TSVs on a back face connection, normal vias on a front face connection and so on) within each layer at positions which are allowed by the copper bond points present at the surface to which the respective vertical interconnect connects. Where a vertical interconnect may be placed within an integrated circuit in each layer thus depends upon the relative positioning of the components of that integrated circuit with respect to the copper bond points for that layer. This can result in a lengthy and laborious design process wherein the system designer must ensure that the positions of the vertical interconnects throughout each layer of the three dimensional integrated circuit are correctly positioned with respect the relevant copper bond points.
Accordingly it would be desirable to provide an improved technique for designing a multiple layer integrated circuit wherein this design compliance burden for the system designer is reduced.